Separable FIR filtering in FPGA and GPU implementations: Energy, performance, and accuracy considerations

Daniel Llamocca, Cesar Carranza, Marios Pattichis

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

20 Citas (Scopus)

Resumen

Digital video processing requires significant hardware resources to achieve acceptable performance. Digital video processing based on dynamic partial reconfiguration (DPR) allows the designers to control resources based on energy, performance, and accuracy considerations. In this paper, we present a dynamically reconfigurable implementation of a 2D FIR filter where the number of coefficients and coefficients values can be varied to control energy, performance, and precision requirements. We also present a high-performance GPU implementation to help understand the trade-offs between these two technologies. Results using a standard example of 2D Difference of Gaussians (DOG) filter indicate that the DPR implementation can deliver real-time performance with energy per frame consumption that is an order of magnitude less than the GPU. On the other hand, at significantly higher energy consumption levels, the GPU implementation can deliver very high performance.

Idioma originalInglés
Título de la publicación alojadaProceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011
Páginas363-368
Número de páginas6
DOI
EstadoPublicada - 2011
Evento21st International Conference on Field Programmable Logic and Applications, FPL 2011 - Chania, Grecia
Duración: 5 set. 20117 set. 2011

Serie de la publicación

NombreProceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011

Conferencia

Conferencia21st International Conference on Field Programmable Logic and Applications, FPL 2011
País/TerritorioGrecia
CiudadChania
Período5/09/117/09/11

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