Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices

G. F.Q. Santillan; D. C. Iparraguirre

Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices

G. F.Q. Santillan, D. C. Iparraguirre

Pontificia Universidad Catolica del Peru

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

1 Cita (Scopus)

Resumen

In this work an FIR filter is designed, combining the systolic architecture with the digit-serial technique. Multipliers are designed with this technique and the accumulator exploits these characteristics avoiding the lack of real-time computing capability and data processing speed. The system can be used in realtime digital signal and image processing applications. The simulation results presented were obtained using the FLEX 10K20 device of Altera.

Idioma original	Español
Título de la publicación alojada	Proceedings of the 3rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications
Páginas	147-150
Número de páginas	4
Estado	Publicada - 1 ene. 1999
Publicado de forma externa	Sí

Citar esto

@inproceedings{2205990ac74d4dc58dca6330bc765ba5,

title = "Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices",

abstract = "In this work an FIR filter is designed, combining the systolic architecture with the digit-serial technique. Multipliers are designed with this technique and the accumulator exploits these characteristics avoiding the lack of real-time computing capability and data processing speed. The system can be used in realtime digital signal and image processing applications. The simulation results presented were obtained using the FLEX 10K20 device of Altera.",

author = "Santillan, {G. F.Q.} and Iparraguirre, {D. C.}",

year = "1999",

month = jan,

day = "1",

language = "Espa{\~n}ol",

pages = "147--150",

booktitle = "Proceedings of the 3rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications",

}

Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices. / Santillan, G. F.Q.; Iparraguirre, D. C.
Proceedings of the 3rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications. 1999. p. 147-150.

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

TY - GEN

T1 - Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices

AU - Santillan, G. F.Q.

AU - Iparraguirre, D. C.

PY - 1999/1/1

Y1 - 1999/1/1

N2 - In this work an FIR filter is designed, combining the systolic architecture with the digit-serial technique. Multipliers are designed with this technique and the accumulator exploits these characteristics avoiding the lack of real-time computing capability and data processing speed. The system can be used in realtime digital signal and image processing applications. The simulation results presented were obtained using the FLEX 10K20 device of Altera.

AB - In this work an FIR filter is designed, combining the systolic architecture with the digit-serial technique. Multipliers are designed with this technique and the accumulator exploits these characteristics avoiding the lack of real-time computing capability and data processing speed. The system can be used in realtime digital signal and image processing applications. The simulation results presented were obtained using the FLEX 10K20 device of Altera.

M3 - Contribución a la conferencia

SP - 147

EP - 150

BT - Proceedings of the 3rd International Workshop on Design of Mixed-Mode Integrated Circuits and Applications

ER -