Real-time digit-serial decimating filter using systolic arrays and implemented in a CPLD

Daniel Iparraguirre-Cardenas, G. F.Q. Santillan

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva


In this paper, a digit-serial decimating filter using a systolic architecture is presented for digit-sizes 1, 2 and 4. The flip-flop's clock enable inputs are used for the multipliers to work at half the clock frequency, so it is possible for the filter to work at a higher frequency than the apparent result of the Timing simulation. The CPLD features are used to increase the clock frequency, as well as the different synthesis options. This design has a real-time computing capability. The architecture has been designed with Max+Plus II 9.01 and simulated using FLEX 10K devices of the Altera family.
Idioma originalEspañol
Título de la publicación alojadaProceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS
EstadoPublicada - 3 dic. 2000
Publicado de forma externa

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