Real-time digit-serial decimating filter using systolic arrays and implemented in a CPLD

Daniel Iparraguirre-Cardenas; G. F.Q. Santillan

Real-time digit-serial decimating filter using systolic arrays and implemented in a CPLD

Daniel Iparraguirre-Cardenas, G. F.Q. Santillan

Pontificia Universidad Catolica del Peru

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

Resumen

In this paper, a digit-serial decimating filter using a systolic architecture is presented for digit-sizes 1, 2 and 4. The flip-flop's clock enable inputs are used for the multipliers to work at half the clock frequency, so it is possible for the filter to work at a higher frequency than the apparent result of the Timing simulation. The CPLD features are used to increase the clock frequency, as well as the different synthesis options. This design has a real-time computing capability. The architecture has been designed with Max+Plus II 9.01 and simulated using FLEX 10K devices of the Altera family.

Idioma original	Español
Título de la publicación alojada	Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS
Estado	Publicada - 3 dic. 2000
Publicado de forma externa	Sí

Citar esto

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title = "Real-time digit-serial decimating filter using systolic arrays and implemented in a CPLD",

abstract = "In this paper, a digit-serial decimating filter using a systolic architecture is presented for digit-sizes 1, 2 and 4. The flip-flop's clock enable inputs are used for the multipliers to work at half the clock frequency, so it is possible for the filter to work at a higher frequency than the apparent result of the Timing simulation. The CPLD features are used to increase the clock frequency, as well as the different synthesis options. This design has a real-time computing capability. The architecture has been designed with Max+Plus II 9.01 and simulated using FLEX 10K devices of the Altera family.",

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Real-time digit-serial decimating filter using systolic arrays and implemented in a CPLD. / Iparraguirre-Cardenas, Daniel; Santillan, G. F.Q.
Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS. 2000.

Producción científica: Capítulo del libro/informe/acta de congreso › Contribución a la conferencia › revisión exhaustiva

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N2 - In this paper, a digit-serial decimating filter using a systolic architecture is presented for digit-sizes 1, 2 and 4. The flip-flop's clock enable inputs are used for the multipliers to work at half the clock frequency, so it is possible for the filter to work at a higher frequency than the apparent result of the Timing simulation. The CPLD features are used to increase the clock frequency, as well as the different synthesis options. This design has a real-time computing capability. The architecture has been designed with Max+Plus II 9.01 and simulated using FLEX 10K devices of the Altera family.

AB - In this paper, a digit-serial decimating filter using a systolic architecture is presented for digit-sizes 1, 2 and 4. The flip-flop's clock enable inputs are used for the multipliers to work at half the clock frequency, so it is possible for the filter to work at a higher frequency than the apparent result of the Timing simulation. The CPLD features are used to increase the clock frequency, as well as the different synthesis options. This design has a real-time computing capability. The architecture has been designed with Max+Plus II 9.01 and simulated using FLEX 10K devices of the Altera family.

M3 - Contribución a la conferencia

BT - Proceedings of the IEEE International Caracas Conference on Devices, Circuits and Systems, ICCDCS

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