TY - GEN
T1 - Properties of high-k materials embedded in low temperature cofired ceramics
AU - Bartsch, Heike
AU - Grieseler, Rolf
AU - Müller, Jens
AU - Barth, Stefan
AU - Pawlowski, Beate
PY - 2010
Y1 - 2010
N2 - Buried capacitors in low temperature cofired ceramics (LTCC) enable increased package density, shorter interconnects and reduced assembly time. The implementation of local patches of (high-k) Sr-doped BaTiO3-tape into a commercial LTCC material (DuPont 951 GreenTape™) using pressure assisted sintering resulted in areal capacitance densities up to 100 pF/mm 2 for 29 μm thick dielectric layers. The influence of the firing conditions, the number of refires and the capacitor assembly on the capacitance was investigated. The k-values range between 161 and 367, depending on sintering conditions and design. That indicates the presence of a permittivity gradient at the contact area between low- and high-k materials, which depends on the metallization geometry and peak temperature. The material distribution at the interface was investigated using EDX analysis to demonstrate the effect of the electrodes as barrier layers to prevent dielectric interactions. Embedded capacitors with a plate area of 5.29 mm2 possessed capacitances greater than 500 pF with tolerances of 8%. This matches the requirements of class K. The insertion loss of rf-components remained below - 15 dB up to 50 GHz, which indicates very good noise suppression behaviour. The capacitors are thus suited for decoupling in the close vicinity of integrated circuits in ceramic packages.
AB - Buried capacitors in low temperature cofired ceramics (LTCC) enable increased package density, shorter interconnects and reduced assembly time. The implementation of local patches of (high-k) Sr-doped BaTiO3-tape into a commercial LTCC material (DuPont 951 GreenTape™) using pressure assisted sintering resulted in areal capacitance densities up to 100 pF/mm 2 for 29 μm thick dielectric layers. The influence of the firing conditions, the number of refires and the capacitor assembly on the capacitance was investigated. The k-values range between 161 and 367, depending on sintering conditions and design. That indicates the presence of a permittivity gradient at the contact area between low- and high-k materials, which depends on the metallization geometry and peak temperature. The material distribution at the interface was investigated using EDX analysis to demonstrate the effect of the electrodes as barrier layers to prevent dielectric interactions. Embedded capacitors with a plate area of 5.29 mm2 possessed capacitances greater than 500 pF with tolerances of 8%. This matches the requirements of class K. The insertion loss of rf-components remained below - 15 dB up to 50 GHz, which indicates very good noise suppression behaviour. The capacitors are thus suited for decoupling in the close vicinity of integrated circuits in ceramic packages.
UR - http://www.scopus.com/inward/record.url?scp=78651296622&partnerID=8YFLogxK
U2 - 10.1109/ESTC.2010.5642935
DO - 10.1109/ESTC.2010.5642935
M3 - Conference contribution
AN - SCOPUS:78651296622
SN - 9781424485536
T3 - Electronics System Integration Technology Conference, ESTC 2010 - Proceedings
BT - Electronics System Integration Technology Conference, ESTC 2010 - Proceedings
T2 - 3rd Electronics System Integration Technology Conference, ESTC 2010
Y2 - 13 September 2010 through 16 September 2010
ER -