TY - JOUR
T1 - PECVD-AlOx/SiNx passivation stacks on silicon
T2 - 4th International Conference on Crystalline Silicon Photovoltaics, SiliconPV 2014
AU - Tofflinger, Jan Amaru
AU - Laades, Abdelazize
AU - Leendertz, Caspar
AU - Montanez, Liz Margarita
AU - Korte, Lars
AU - Sturzebecher, Uta
AU - Sperlich, Hans Peter
AU - Rech, Bernd
N1 - Publisher Copyright:
© 2014 The Authors. Published by Elsevier Ltd.
PY - 2014
Y1 - 2014
N2 - The charge dynamics and the interface defect state density of AlOx/SiNx passivation stacks deposited by plasma-enhanced chemical vapor deposition (PECVD) on crystalline silicon (c-Si) wafers are investigated. High frequency (1 MHz) capacitance voltage (C-V) measurements were performed on stacks in the as deposited state and after an annealing step. C-V sweeps reveal an initially high negative charge density for the as deposited sample, activated by the thermal budget during SiNx deposition. However, this charge state is unstable and reduced owning to electron detrapping and emission into the c-Si upon applying moderate voltages. In the annealed sample, the AlOx/SiNx stack has a stable negative fixed charge. Both for as deposited and for annealed samples, applying a positive or negative constant gate voltage stress (Vstress) enhances or reduces the negative effective charge density (Qox,eff), respectively. Injection of charges from the c-Si into traps in the AlOx/SiNx stack is identified as the mechanism responsible for this behavior. We conclude that in addition to fixed negative charges trapping of negative charges near the interface is a crucial mechanism contributing to the total effective negative charge of the stack. Their contribution depends on the temperature and duration of the thermal treatment. Additionally, a large Vstress leads to generation of additional Si dangling bond defects over the entire c-Si bang gap at the c-Si/AlOx interface.
AB - The charge dynamics and the interface defect state density of AlOx/SiNx passivation stacks deposited by plasma-enhanced chemical vapor deposition (PECVD) on crystalline silicon (c-Si) wafers are investigated. High frequency (1 MHz) capacitance voltage (C-V) measurements were performed on stacks in the as deposited state and after an annealing step. C-V sweeps reveal an initially high negative charge density for the as deposited sample, activated by the thermal budget during SiNx deposition. However, this charge state is unstable and reduced owning to electron detrapping and emission into the c-Si upon applying moderate voltages. In the annealed sample, the AlOx/SiNx stack has a stable negative fixed charge. Both for as deposited and for annealed samples, applying a positive or negative constant gate voltage stress (Vstress) enhances or reduces the negative effective charge density (Qox,eff), respectively. Injection of charges from the c-Si into traps in the AlOx/SiNx stack is identified as the mechanism responsible for this behavior. We conclude that in addition to fixed negative charges trapping of negative charges near the interface is a crucial mechanism contributing to the total effective negative charge of the stack. Their contribution depends on the temperature and duration of the thermal treatment. Additionally, a large Vstress leads to generation of additional Si dangling bond defects over the entire c-Si bang gap at the c-Si/AlOx interface.
KW - Aluminum oxide
KW - Capacitace voltage
KW - Silicon
KW - Silicon nitride
KW - Surface passivation
UR - http://www.scopus.com/inward/record.url?scp=84922281200&partnerID=8YFLogxK
U2 - 10.1016/j.egypro.2014.08.068
DO - 10.1016/j.egypro.2014.08.068
M3 - Conference article
AN - SCOPUS:84922281200
SN - 1876-6102
VL - 55
SP - 845
EP - 854
JO - Energy Procedia
JF - Energy Procedia
Y2 - 25 March 2014 through 27 March 2014
ER -