TY - GEN
T1 - Exploring area and total wirelength using a cell merging technique
AU - Albinagorta, Kevin A.Caceres
AU - Conceicao, Calebe
AU - Cardenas, Carlos Silva
AU - Reis, Ricardo
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate's Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5 and 4.2 on average, respectively.
AB - The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate's Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5 and 4.2 on average, respectively.
KW - Layout Generator
KW - Logic Synthesis
KW - Physical Synthesis
KW - SCCG
UR - http://www.scopus.com/inward/record.url?scp=85076816631&partnerID=8YFLogxK
U2 - 10.1109/VLSI-SoC.2019.8920337
DO - 10.1109/VLSI-SoC.2019.8920337
M3 - Conference contribution
AN - SCOPUS:85076816631
T3 - IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
SP - 329
EP - 334
BT - VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings
A2 - Metzler, Carolina
A2 - De Micheli, Giovanni
A2 - Gaillardon, Pierre-Emmanuel
A2 - Silva-Cardenas, Carlos
A2 - Reis, Ricardo
PB - IEEE Computer Society
T2 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019
Y2 - 6 October 2019 through 9 October 2019
ER -