Design of a CMOS cross-coupled voltage doubler

Luis Rodriguez, Erick Raygada, Carlos Silva, Julio Saldana

Producción científica: Capítulo del libro/informe/acta de congresoContribución a la conferenciarevisión exhaustiva

3 Citas (Scopus)

Resumen

This paper describes a design procedure for a CMOS voltage doubler. Test-bench circuit are used to verify the performance of the design. Several equations that relate performance parameters with design variables are presented. This set of equations considers both transient and steady state behavior. Various known energy losses such as switching and conduction losses were taken into account for transistors sizing. The effects of the characteristics of the pump capacitors are analyzed and evaluated through electrical simulations. A design example based on AMS 0.35μm process is presented.

Idioma originalInglés
Título de la publicación alojadaProceedings of the 2016 IEEE ANDESCON, ANDESCON 2016
EditorialInstitute of Electrical and Electronics Engineers Inc.
ISBN (versión digital)9781509025312
DOI
EstadoPublicada - 27 ene. 2017
Evento2016 IEEE ANDESCON, ANDESCON 2016 - Arequipa, Perú
Duración: 19 oct. 201621 oct. 2016

Serie de la publicación

NombreProceedings of the 2016 IEEE ANDESCON, ANDESCON 2016

Conferencia

Conferencia2016 IEEE ANDESCON, ANDESCON 2016
País/TerritorioPerú
CiudadArequipa
Período19/10/1621/10/16

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