TY - GEN
T1 - An efficient hardware architecture of the H.264/AVC half and quarter-pixel motion estimation for real-time high-definition video streams
AU - Castillo, Ernesto Villegas
AU - Cárdenas, Carlos Silva
AU - Jara, Mario Raffo
PY - 2012
Y1 - 2012
N2 - The H.264/AVC is the newest digital video compression standard developed by the Joint Video Team (JVT). This standard includes new algorithms as the Fractional Motion Estimation that enhances the coding efficiency and compression rate of video sequences implicating a higher computational complexity. The H.264/AVC is most commonly used for High Definition Video (HDTV) real-time broadcasting for Digital Television, demanding hardware implementations of the CODECs. In this work, an efficient hardware architecture for the Half and Quarter-Pixel Motion Estimation is proposed. The design was described using VHDL and synthesized to the ALTERA Cyclone II FPGA being able to process real time HDTV (1920x1080) video streams (30 frames per second). The synthesis results establish a maximum frequency of 105.22 MHz after applying optimization methods, being able to process 41.62 HDTV frames per second (fps).
AB - The H.264/AVC is the newest digital video compression standard developed by the Joint Video Team (JVT). This standard includes new algorithms as the Fractional Motion Estimation that enhances the coding efficiency and compression rate of video sequences implicating a higher computational complexity. The H.264/AVC is most commonly used for High Definition Video (HDTV) real-time broadcasting for Digital Television, demanding hardware implementations of the CODECs. In this work, an efficient hardware architecture for the Half and Quarter-Pixel Motion Estimation is proposed. The design was described using VHDL and synthesized to the ALTERA Cyclone II FPGA being able to process real time HDTV (1920x1080) video streams (30 frames per second). The synthesis results establish a maximum frequency of 105.22 MHz after applying optimization methods, being able to process 41.62 HDTV frames per second (fps).
UR - http://www.scopus.com/inward/record.url?scp=84860466688&partnerID=8YFLogxK
U2 - 10.1109/LASCAS.2012.6180302
DO - 10.1109/LASCAS.2012.6180302
M3 - Conference contribution
AN - SCOPUS:84860466688
SN - 9781467312080
T3 - 2012 IEEE 3rd Latin American Symposium on Circuits and Systems, LASCAS 2012 - Conference Proceedings
BT - 2012 IEEE 3rd Latin American Symposium on Circuits and Systems, LASCAS 2012 - Conference Proceedings
T2 - 2012 IEEE 3rd Latin American Symposium on Circuits and Systems, LASCAS 2012
Y2 - 29 February 2012 through 2 March 2012
ER -