TY - GEN
T1 - A scalable architecture for implementing the fast discrete periodic radon transform for prime sized images
AU - Carranza, Cesar
AU - Llamocca, Daniel
AU - Pattichis, Marios
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/1/28
Y1 - 2014/1/28
N2 - The Discrete Periodic Radon Transform (DPRT) has many important applications in image processing that are associated with reconstructing objects from projections (e.g., computed tomography [1]) or image restoration (e.g., [2]). Thus, there is strong interest in the development of fast algorithms and architectures for computing the DPRT. This paper introduces a scalable hardware architecture and associated algorithm for computing the DPRT for prime-sized images. For square images of size N × N, N prime, the DPRT requires N2 (N - 1) additions for calculating image projections along a minimal number of prime directions. The proposed approach can compute the DPRT in [N/2h] N + 2N + h clock cycles, h = 1,..., [log2 N], where h is a scaling factor that is used to control the required hardware resources that are needed to implement the fast DPRT. Compared to previous approaches, a fundamental contribution of the proposed architecture is that it allows effective implementations based on different constraints on the resources.
AB - The Discrete Periodic Radon Transform (DPRT) has many important applications in image processing that are associated with reconstructing objects from projections (e.g., computed tomography [1]) or image restoration (e.g., [2]). Thus, there is strong interest in the development of fast algorithms and architectures for computing the DPRT. This paper introduces a scalable hardware architecture and associated algorithm for computing the DPRT for prime-sized images. For square images of size N × N, N prime, the DPRT requires N2 (N - 1) additions for calculating image projections along a minimal number of prime directions. The proposed approach can compute the DPRT in [N/2h] N + 2N + h clock cycles, h = 1,..., [log2 N], where h is a scaling factor that is used to control the required hardware resources that are needed to implement the fast DPRT. Compared to previous approaches, a fundamental contribution of the proposed architecture is that it allows effective implementations based on different constraints on the resources.
KW - Discrete Periodic Radon Transform (DPRT)
KW - FPGA
KW - Parallel Architecture
KW - Scalable Architecture
KW - VLSI
UR - http://www.scopus.com/inward/record.url?scp=84949928715&partnerID=8YFLogxK
U2 - 10.1109/ICIP.2014.7025241
DO - 10.1109/ICIP.2014.7025241
M3 - Conference contribution
AN - SCOPUS:84949928715
T3 - 2014 IEEE International Conference on Image Processing, ICIP 2014
SP - 1208
EP - 1212
BT - 2014 IEEE International Conference on Image Processing, ICIP 2014
PB - Institute of Electrical and Electronics Engineers Inc.
ER -