A placement tool for a NoC-based dynamically reconfigurable system

In the last years, Field programmable gate-arrays (FPGAs) with partial reconfiguration capabilities have raised interest in the implementation of dynamically reconfigurable systems. It has not become a mainstream activity though, due to the lack of solid design methodologies and associated tools. One of the approaches aimed to free the designer of lower level implementation details is to use structured communication resources to provide the interaction between reconfigurable partitions (modules). The architecture of a network-on-chip (NoC) based dynamically reconfigurable system and a placement tool, which automatically places all of its modules, is presented. The tool takes the partitioned design information and the restrictions imposed by the device family architecture into consideration. The basics of the placement algorithm and a study-case as an example are presented.