A highly parallel 4K real-time HEVC fractional motion estimation architecture for FPGA implementation

HEVC is the newest standard developed by the Joint Collaborative Team on Video Coding (JCT-VC), mainly characterized by improving the encoding performance and efficiency in almost 50% of its predecessor, H.264/AVC for the same video quality. HEVC is also characterized for targeting Ultra High Definition (UHD) video streams e.g. 4k and 8k resolutions. These improvements resulted from the enhance of encoding processes complexity, which also brings the necessity of more computational resources for its implementation. One of the hot spots in HEVC Encoding is the Fractional Motion Estimation (FME) process, which significantly improves the video compression efficiency at the expense of 40-60% of encoding time in the ITU-T standard coding software. In order to optimize this processing time and make it suitable for Real-Time UHD Video applications, this work proposes a highly parallel Half and Quarter-Pixel Accurate FME architecture targeting FPGA devices. The architecture was described using VHDL and synthesized for the Altera Cyclone IV, V and Arria II FPGA families. The results established a maximum frequency of 298 MHz being able to process 4K (3840×2160) Video Streaming @38fps.