TY - GEN
T1 - A general-purpose dynamically reconfigurable SVM
AU - Filho, Jonas Gomes
AU - Raffo, Mario
AU - Strum, Marius
AU - Chau, Wang Jiang
PY - 2010
Y1 - 2010
N2 - This paper presents an hardware implementation of the Sequential Minimal Optimization (SMO) for the Support Vector Machine (SVM) training phase. A general-purpose reconfigurable architecture, aimed to partial reconfiguration FPGAs, is developed, i.e., it supports different sizes of training sets, with wide-range number of samples and elements. The effects of fixed-point implementation are analyzed and data on area and frequency targeting the Xilinx Virtex-IV XC4VLX25 FPGA are provided. The architecture was able to perform the training in different learning benchmarks and the reconfigurable architecture was able to save 22.38% of FPGA's area.
AB - This paper presents an hardware implementation of the Sequential Minimal Optimization (SMO) for the Support Vector Machine (SVM) training phase. A general-purpose reconfigurable architecture, aimed to partial reconfiguration FPGAs, is developed, i.e., it supports different sizes of training sets, with wide-range number of samples and elements. The effects of fixed-point implementation are analyzed and data on area and frequency targeting the Xilinx Virtex-IV XC4VLX25 FPGA are provided. The architecture was able to perform the training in different learning benchmarks and the reconfigurable architecture was able to save 22.38% of FPGA's area.
UR - http://www.scopus.com/inward/record.url?scp=77954451151&partnerID=8YFLogxK
U2 - 10.1109/SPL.2010.5483031
DO - 10.1109/SPL.2010.5483031
M3 - Conference contribution
AN - SCOPUS:77954451151
SN - 9781424470891
T3 - 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings
SP - 107
EP - 112
BT - 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings
T2 - 6th Southern Programmable Logic Conference, SPL 2010
Y2 - 24 March 2010 through 26 March 2010
ER -