A flexible UVM-based verification framework reusable with avalon, AHB, AXI and wishbone bus interfaces for an AES encryption module

The fast and continuous development of digital circuits lead to complex and unpredictable designs which have to be submitted under high-standard verification processes. Furthermore, not only the core modules have evolved over the time, but also the communication interfaces; consequently, there are several of them that implement different features. Conventionally, the interfaces are selected according to the system requirements of power, speed, latency, number of peripherals, etc. This causes a single unit-level design to be implemented along with different communication interfaces in multiple systems that differ on their specifications. Besides, for all of those scenarios the verification process at the system-level must be done. For this reason, flexibility has become a key point for an efficient verification framework in order to balance between market demands and time-to-market. This paper proposes a UVM-Based functional verification framework reusable with Avalon (a parameterized bus from Altera), AHB, AXI (some of the most representative buses from ARM) and Wishbone (the most utilized portable IP core for diverse purposes) bus interfaces. This election is based on the fact that all of these buses are highly used for high performance and enhanced bandwidth applications, making the proposed verification framework more likely to be reused in most systems since it is capable of handling all of these four different communication protocols.