Early Safety Analysis of Software Test Libraries for Automotive SoCs based on Virtual Prototyping

Emerging edge technologies such as Advanced Driver Assistance Systems and autonomous vehicles demand exceptional dependability to mitigate risks and ensure human safety. To address these challenges, industry standards like ISO 26262 enforce rigorous safety requirements for automotive systems. While EDA tools are advancing to support safer SoC designs, the potential of Virtual Prototyping for developing and validating safety mechanisms remains underexploited. This paper introduces a fully SystemC/TLM2.0-based virtual prototype of an automotive-grade SoC (AutoSoC), designed to support early-stage design. The prototype integrates an instruction set simulator, memory, a UART peripheral connected to a terminal interface, and a custom CAN controller. It enables early-stage validation of the AutoSoC software stack and provides debugging capabilities for monitoring internal states and peripheral interactions. Simulation of the Software Test Library (STL) on the OpenRISC 1000 CPU revealed behavioral discrepancies in register operations compared to RT-level models, highlighting the VP’s effectiveness for architectural exploration. Furthermore, simulating STL protection of automotive peripherals such as the CAN controller supports iterative refinement of the high-level model to ensure functional and register-level accuracy. By reducing reliance on RT-level models during early development phases, our approach accelerates design cycles and facilitates the early detection of architectural vulnerabilities.