Design of a 32nm Ultra-Low Power 6T SRAM Cell Analyzing Emerging Technologies such as FinFET, TFET, and CNFET for energy-efficient applications

This work presents the design, simulation, and comparative analysis of a 6-transistor (6T) static random-access memory (SRAM) cell optimized for ultra-low-power operation. Emerging device technologies-Fin Field-Effect Transistor (FinFET), Tunnel Field-Effect Transistor (TFET), and Carbon Nanotube Field-Effect Transistor (CNFET)-are evaluated individually and in hybrid configurations to overcome the limitations of conventional CMOS SRAM cells. Device-level models are calibrated to ensure fair comparison, matching leakage currents and parasitic capacitances. Using NGSPICE and HSPICE simulations at subthreshold supply voltages (0.6-0.8 V), we measure static, dynamic, and total power consumption for each configuration. Results show that the FinFET-TFET hybrid achieves the lowest total power dissipation, combining the low leakage of TFETs with the high speed and channel control of FinFETs, making it suitable for energy-constrained applications such as IoT and implantable devices.