Robust functional verification framework based in uvm applied to an aes encryption module

Frank Plasencia-Balabarca, Edward Mitacc-Meza, Mario Raffo-Jara, Carlos Silva-Cardenas

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations


This Since the past century, the digital design industry has performed an outstanding role in the development of electronics. Hence, a great variety of designs are developed daily, these designs must be submitted to high standards of verification in order to ensure the 100% of reliability and the achievement of all design requirements. The Universal Verification Methodology (UVM) is the current standard at the industry for the verification process due to its reusability, scalability, time-efficiency and feasibility of handling high-level designs. This research proposes a functional verification framework using UVM for an AES encryption module based on a very detailed and robust verification plan. This document describes the complete verification process as done in the industry for a popular module used in information-security applications in the field of cryptography, defining the basis for future projects. The overall results show the achievement of the high verification standards required in industry applications and highlight the advantages of UVM against System Verilog-based functional verification and direct verification methodologies previously developed for the AES module.

Original languageEnglish
Title of host publication2018 New Generation of CAS, NGCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)9781538676813
StatePublished - 10 Dec 2018
Event2018 New Generation of CAS, NGCAS 2018 - Valletta, Malta
Duration: 20 Nov 201823 Nov 2018

Publication series

Name2018 New Generation of CAS, NGCAS 2018


Conference2018 New Generation of CAS, NGCAS 2018


  • AES Encryption module
  • Functional Verification
  • UVM
  • Verification Framework


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