Reduced power consumption in the FPGA-based Universal Link for LVDS communications

Luis Sanchez; Giancarlo Patino; Victor Murray; James Lyke

doi:10.1109/LASCAS.2016.7451065

Reduced power consumption in the FPGA-based Universal Link for LVDS communications

Luis Sanchez
, Giancarlo Patino
, Victor Murray
, James Lyke

University of Engineering and Technology UTEC
The University of New Mexico
Air Force Research Laboratory

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

We present a novel version of the FPGA-based Universal Link for LVDS (low-voltage differential signaling) communications that reduces the power consumption by sending the information only when a new data is input. In the a regular LVDS protocol, 4 wires are required for a full duplex communication. The aim of the Universal Link is to reduce the amount of wires in the network by sending data from N signal through a single connection. These new approach reduces the number of bits transmitted to 84% of the original system, when N = 2, and up to 23% for N > 130. Also, the sampling frequency is considerable reduced.

Original language	English
Title of host publication	LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference
Editors	Andreas G. Andreou, Pedro Julian
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	283-286
Number of pages	4
ISBN (Electronic)	9781467378352
DOIs	https://doi.org/10.1109/LASCAS.2016.7451065
State	Published - 11 Apr 2016
Externally published	Yes
Event	7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016 - Florianopolis, Brazil Duration: 27 Feb 2016 → 1 Mar 2016

Publication series

Name	LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference

Conference

Conference	7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016
Country/Territory	Brazil
City	Florianopolis
Period	27/02/16 → 1/03/16

Keywords

LVDS
Spacewire
Universal Link

Access to Document

10.1109/LASCAS.2016.7451065

Cite this

Sanchez, L., Patino, G., Murray, V., & Lyke, J. (2016). Reduced power consumption in the FPGA-based Universal Link for LVDS communications. In A. G. Andreou, & P. Julian (Eds.), LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference (pp. 283-286). Article 7451065 (LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/LASCAS.2016.7451065

Sanchez, Luis ; Patino, Giancarlo ; Murray, Victor et al. / Reduced power consumption in the FPGA-based Universal Link for LVDS communications. LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference. editor / Andreas G. Andreou ; Pedro Julian. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 283-286 (LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference).

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title = "Reduced power consumption in the FPGA-based Universal Link for LVDS communications",

abstract = "We present a novel version of the FPGA-based Universal Link for LVDS (low-voltage differential signaling) communications that reduces the power consumption by sending the information only when a new data is input. In the a regular LVDS protocol, 4 wires are required for a full duplex communication. The aim of the Universal Link is to reduce the amount of wires in the network by sending data from N signal through a single connection. These new approach reduces the number of bits transmitted to 84\% of the original system, when N = 2, and up to 23\% for N > 130. Also, the sampling frequency is considerable reduced.",

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author = "Luis Sanchez and Giancarlo Patino and Victor Murray and James Lyke",

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language = "English",

series = "LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference",

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Sanchez, L, Patino, G, Murray, V & Lyke, J 2016, Reduced power consumption in the FPGA-based Universal Link for LVDS communications. in AG Andreou & P Julian (eds), LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference., 7451065, LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference, Institute of Electrical and Electronics Engineers Inc., pp. 283-286, 7th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2016, Florianopolis, Brazil, 27/02/16. https://doi.org/10.1109/LASCAS.2016.7451065

Reduced power consumption in the FPGA-based Universal Link for LVDS communications. / Sanchez, Luis; Patino, Giancarlo; Murray, Victor et al.
LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference. ed. / Andreas G. Andreou; Pedro Julian. Institute of Electrical and Electronics Engineers Inc., 2016. p. 283-286 7451065 (LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Murray, Victor

AU - Lyke, James

PY - 2016/4/11

Y1 - 2016/4/11

N2 - We present a novel version of the FPGA-based Universal Link for LVDS (low-voltage differential signaling) communications that reduces the power consumption by sending the information only when a new data is input. In the a regular LVDS protocol, 4 wires are required for a full duplex communication. The aim of the Universal Link is to reduce the amount of wires in the network by sending data from N signal through a single connection. These new approach reduces the number of bits transmitted to 84% of the original system, when N = 2, and up to 23% for N > 130. Also, the sampling frequency is considerable reduced.

AB - We present a novel version of the FPGA-based Universal Link for LVDS (low-voltage differential signaling) communications that reduces the power consumption by sending the information only when a new data is input. In the a regular LVDS protocol, 4 wires are required for a full duplex communication. The aim of the Universal Link is to reduce the amount of wires in the network by sending data from N signal through a single connection. These new approach reduces the number of bits transmitted to 84% of the original system, when N = 2, and up to 23% for N > 130. Also, the sampling frequency is considerable reduced.

KW - LVDS

KW - Spacewire

KW - Universal Link

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DO - 10.1109/LASCAS.2016.7451065

M3 - Conference contribution

AN - SCOPUS:84982796220

T3 - LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference

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BT - LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference

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Sanchez L, Patino G, Murray V, Lyke J. Reduced power consumption in the FPGA-based Universal Link for LVDS communications. In Andreou AG, Julian P, editors, LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference. Institute of Electrical and Electronics Engineers Inc. 2016. p. 283-286. 7451065. (LASCAS 2016 - 7th IEEE Latin American Symposium on Circuits and Systems, R9 IEEE CASS Flagship Conference). doi: 10.1109/LASCAS.2016.7451065

Reduced power consumption in the FPGA-based Universal Link for LVDS communications

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Keywords

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