TY - GEN
T1 - On the jitter-to-fast-clock-period ratio in oscillator-based true random number generators
AU - Bejar, Eduardo
AU - Saldana, Julio
AU - Raygada, Erick
AU - Silva, Carlos
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/2
Y1 - 2017/7/2
N2 - This paper presents a new interpretation of the jitter-to-fast-clock-period ratio in oscillator-based true random number generators (TRNGs). This parameter, that can be employed to characterize the output random bit stream quality at the circuit level, is expressed in this paper as the product of two other parameters: phase jitter and slow-clock-period-to-fast-clock-period ratio. Based on this new expression, a strategy to increase the TRNG throughput without compromising the randomness of the output bit stream is proposed. As an example, it is presented the design of a Schmitt trigger oscillator-based TRNG in an AMS 0.35μm CMOS process, which consumes 0.6 mW, occupies 0.0396 mm2 die area and generates 400 kbps random bit streams. The obtained random sequences were tested using the National Institute of Standards and Technology (NIST) statistical test suite for random number generators validation.
AB - This paper presents a new interpretation of the jitter-to-fast-clock-period ratio in oscillator-based true random number generators (TRNGs). This parameter, that can be employed to characterize the output random bit stream quality at the circuit level, is expressed in this paper as the product of two other parameters: phase jitter and slow-clock-period-to-fast-clock-period ratio. Based on this new expression, a strategy to increase the TRNG throughput without compromising the randomness of the output bit stream is proposed. As an example, it is presented the design of a Schmitt trigger oscillator-based TRNG in an AMS 0.35μm CMOS process, which consumes 0.6 mW, occupies 0.0396 mm2 die area and generates 400 kbps random bit streams. The obtained random sequences were tested using the National Institute of Standards and Technology (NIST) statistical test suite for random number generators validation.
UR - http://www.scopus.com/inward/record.url?scp=85047348409&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2017.8292100
DO - 10.1109/ICECS.2017.8292100
M3 - Conference contribution
AN - SCOPUS:85047348409
T3 - ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems
SP - 243
EP - 246
BT - ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017
Y2 - 5 December 2017 through 8 December 2017
ER -