Implementation of split-radix Fast Fourier Transform on FPGA

Cynthia Watanabe; Carlos Silva; Joel Muñoz

doi:10.1109/SPL.2010.5483018

Implementation of split-radix Fast Fourier Transform on FPGA

Cynthia Watanabe, Carlos Silva, Joel Muñoz

Sección de Ingeniería de Telecomunicaciones

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Nowadays, portable systems are developed especially for signal processing, where the principal challenge is to find circuits with less area and power consumption. One of the most powerful tools in the area of Signal Processing is the Fast Fourier Transform (FFT). Many algorithms have been developed to improve its computation time; one of them is the Split Radix Fast Fourier Transform (SRFFT) which reduces the number of complex computation. Therefore, a new architecture is proposed to compute the SRFFT. Although the runtime of this design is high, it has some important profits like a flexible number of inputs N=2^P; few resources required such as combinational functions, logic registers and memory.

Original language	English
Title of host publication	6th Southern Programmable Logic Conference, SPL 2010 - Proceedings
Pages	167-170
Number of pages	4
DOIs	https://doi.org/10.1109/SPL.2010.5483018
State	Published - 2010
Event	6th Southern Programmable Logic Conference, SPL 2010 - Ipojuca, Brazil Duration: 24 Mar 2010 → 26 Mar 2010

Publication series

Name	6th Southern Programmable Logic Conference, SPL 2010 - Proceedings

Conference

Conference	6th Southern Programmable Logic Conference, SPL 2010
Country/Territory	Brazil
City	Ipojuca
Period	24/03/10 → 26/03/10

Access to Document

10.1109/SPL.2010.5483018

Cite this

@inproceedings{33319f713bab4219b82b809b58685a26,

title = "Implementation of split-radix Fast Fourier Transform on FPGA",

abstract = "Nowadays, portable systems are developed especially for signal processing, where the principal challenge is to find circuits with less area and power consumption. One of the most powerful tools in the area of Signal Processing is the Fast Fourier Transform (FFT). Many algorithms have been developed to improve its computation time; one of them is the Split Radix Fast Fourier Transform (SRFFT) which reduces the number of complex computation. Therefore, a new architecture is proposed to compute the SRFFT. Although the runtime of this design is high, it has some important profits like a flexible number of inputs N=2P; few resources required such as combinational functions, logic registers and memory.",

author = "Cynthia Watanabe and Carlos Silva and Joel Mu{\~n}oz",

year = "2010",

doi = "10.1109/SPL.2010.5483018",

language = "English",

isbn = "9781424470891",

series = "6th Southern Programmable Logic Conference, SPL 2010 - Proceedings",

pages = "167--170",

booktitle = "6th Southern Programmable Logic Conference, SPL 2010 - Proceedings",

note = "6th Southern Programmable Logic Conference, SPL 2010 ; Conference date: 24-03-2010 Through 26-03-2010",

}

Watanabe, C, Silva, C & Muñoz, J 2010, Implementation of split-radix Fast Fourier Transform on FPGA. in 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings., 5483018, 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings, pp. 167-170, 6th Southern Programmable Logic Conference, SPL 2010, Ipojuca, Brazil, 24/03/10. https://doi.org/10.1109/SPL.2010.5483018

Implementation of split-radix Fast Fourier Transform on FPGA. / Watanabe, Cynthia; Silva, Carlos; Muñoz, Joel.
6th Southern Programmable Logic Conference, SPL 2010 - Proceedings. 2010. p. 167-170 5483018 (6th Southern Programmable Logic Conference, SPL 2010 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Implementation of split-radix Fast Fourier Transform on FPGA

AU - Watanabe, Cynthia

AU - Silva, Carlos

AU - Muñoz, Joel

PY - 2010

Y1 - 2010

N2 - Nowadays, portable systems are developed especially for signal processing, where the principal challenge is to find circuits with less area and power consumption. One of the most powerful tools in the area of Signal Processing is the Fast Fourier Transform (FFT). Many algorithms have been developed to improve its computation time; one of them is the Split Radix Fast Fourier Transform (SRFFT) which reduces the number of complex computation. Therefore, a new architecture is proposed to compute the SRFFT. Although the runtime of this design is high, it has some important profits like a flexible number of inputs N=2P; few resources required such as combinational functions, logic registers and memory.

AB - Nowadays, portable systems are developed especially for signal processing, where the principal challenge is to find circuits with less area and power consumption. One of the most powerful tools in the area of Signal Processing is the Fast Fourier Transform (FFT). Many algorithms have been developed to improve its computation time; one of them is the Split Radix Fast Fourier Transform (SRFFT) which reduces the number of complex computation. Therefore, a new architecture is proposed to compute the SRFFT. Although the runtime of this design is high, it has some important profits like a flexible number of inputs N=2P; few resources required such as combinational functions, logic registers and memory.

UR - http://www.scopus.com/inward/record.url?scp=77954450404&partnerID=8YFLogxK

U2 - 10.1109/SPL.2010.5483018

DO - 10.1109/SPL.2010.5483018

M3 - Conference contribution

AN - SCOPUS:77954450404

SN - 9781424470891

T3 - 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings

SP - 167

EP - 170

BT - 6th Southern Programmable Logic Conference, SPL 2010 - Proceedings

T2 - 6th Southern Programmable Logic Conference, SPL 2010

Y2 - 24 March 2010 through 26 March 2010

ER -

Implementation of split-radix Fast Fourier Transform on FPGA

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this