Flexible and configurable integer 1-D discrete wavelet transform architecture in FPGAs using digit-serial technique

G. F.Q. Santillan; Daniel Iparraguirre-Cardenas

Flexible and configurable integer 1-D discrete wavelet transform architecture in FPGAs using digit-serial technique

G. F.Q. Santillan
, Daniel Iparraguirre-Cardenas

Pontificia Universidad Católica del Perú

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The presented architecture allows to configure the discrete 1-D Wavelet transform (DWT) computing (number of samples and number of octaves) from the outside and verifies if the given configuration is a right option before beginning the transform process. The reached configuration is not missed when the process is finished and can be used again for another data sequence without the need of a reset. This is useful for expanding this architecture towards the 2-D DWT. The architecture has been compiled on the Max+Plus II environment for FLEX 10K devices with different types of synthesis. It was described using AHDL (Altera Hardware Description Language) in a parameterized format, which facilitates the implementation of the same architecture with different characteristics.

Original language	Spanish
Title of host publication	IEEE International Symposium on Industrial Electronics
Pages	607-612
Number of pages	6
Volume	2
State	Published - 1 Jan 2000
Externally published	Yes

Cite this

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title = "Flexible and configurable integer 1-D discrete wavelet transform architecture in FPGAs using digit-serial technique",

abstract = "The presented architecture allows to configure the discrete 1-D Wavelet transform (DWT) computing (number of samples and number of octaves) from the outside and verifies if the given configuration is a right option before beginning the transform process. The reached configuration is not missed when the process is finished and can be used again for another data sequence without the need of a reset. This is useful for expanding this architecture towards the 2-D DWT. The architecture has been compiled on the Max+Plus II environment for FLEX 10K devices with different types of synthesis. It was described using AHDL (Altera Hardware Description Language) in a parameterized format, which facilitates the implementation of the same architecture with different characteristics.",

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N2 - The presented architecture allows to configure the discrete 1-D Wavelet transform (DWT) computing (number of samples and number of octaves) from the outside and verifies if the given configuration is a right option before beginning the transform process. The reached configuration is not missed when the process is finished and can be used again for another data sequence without the need of a reset. This is useful for expanding this architecture towards the 2-D DWT. The architecture has been compiled on the Max+Plus II environment for FLEX 10K devices with different types of synthesis. It was described using AHDL (Altera Hardware Description Language) in a parameterized format, which facilitates the implementation of the same architecture with different characteristics.

AB - The presented architecture allows to configure the discrete 1-D Wavelet transform (DWT) computing (number of samples and number of octaves) from the outside and verifies if the given configuration is a right option before beginning the transform process. The reached configuration is not missed when the process is finished and can be used again for another data sequence without the need of a reset. This is useful for expanding this architecture towards the 2-D DWT. The architecture has been compiled on the Max+Plus II environment for FLEX 10K devices with different types of synthesis. It was described using AHDL (Altera Hardware Description Language) in a parameterized format, which facilitates the implementation of the same architecture with different characteristics.

M3 - Contribución a la conferencia

VL - 2

SP - 607

EP - 612

BT - IEEE International Symposium on Industrial Electronics

ER -