Exploring area and total wirelength using a cell merging technique

Kevin A.Caceres Albinagorta, Calebe Conceicao, Carlos Silva Cardenas, Ricardo Reis

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate's Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5 and 4.2 on average, respectively.

Original languageEnglish
Title of host publicationVLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings
EditorsCarolina Metzler, Giovanni De Micheli, Pierre-Emmanuel Gaillardon, Carlos Silva-Cardenas, Ricardo Reis
PublisherIEEE Computer Society
Pages329-334
Number of pages6
ISBN (Electronic)9781728139159
DOIs
StatePublished - Oct 2019
Event27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 - Cuzco, Peru
Duration: 6 Oct 20199 Oct 2019

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Volume2019-October
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Conference

Conference27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019
Country/TerritoryPeru
CityCuzco
Period6/10/199/10/19

Keywords

  • Layout Generator
  • Logic Synthesis
  • Physical Synthesis
  • SCCG

Fingerprint

Dive into the research topics of 'Exploring area and total wirelength using a cell merging technique'. Together they form a unique fingerprint.

Cite this