Exploring area and total wirelength using a cell merging technique

Kevin A.Caceres Albinagorta; Calebe Conceicao; Carlos Silva Cardenas; Ricardo Reis

doi:10.1109/VLSI-SoC.2019.8920337

Exploring area and total wirelength using a cell merging technique

Kevin A.Caceres Albinagorta, Calebe Conceicao, Carlos Silva Cardenas, Ricardo Reis

Sección de Ingeniería de Telecomunicaciones

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate's Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5 and 4.2 on average, respectively.

Original language	English
Title of host publication	VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings
Editors	Carolina Metzler, Giovanni De Micheli, Pierre-Emmanuel Gaillardon, Carlos Silva-Cardenas, Ricardo Reis
Publisher	IEEE Computer Society
Pages	329-334
Number of pages	6
ISBN (Electronic)	9781728139159
DOIs	https://doi.org/10.1109/VLSI-SoC.2019.8920337
State	Published - Oct 2019
Event	27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 - Cuzco, Peru Duration: 6 Oct 2019 → 9 Oct 2019

Publication series

Name	IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
Volume	2019-October
ISSN (Print)	2324-8432
ISSN (Electronic)	2324-8440

Conference

Conference	27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019
Country/Territory	Peru
City	Cuzco
Period	6/10/19 → 9/10/19

Keywords

Layout Generator
Logic Synthesis
Physical Synthesis
SCCG

Access to Document

10.1109/VLSI-SoC.2019.8920337

Cite this

Albinagorta, K. A. C., Conceicao, C., Cardenas, C. S., & Reis, R. (2019). Exploring area and total wirelength using a cell merging technique. In C. Metzler, G. De Micheli, P.-E. Gaillardon, C. Silva-Cardenas, & R. Reis (Eds.), VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings (pp. 329-334). Article 8920337 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2019-October). IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2019.8920337

Albinagorta, Kevin A.Caceres ; Conceicao, Calebe ; Cardenas, Carlos Silva et al. / Exploring area and total wirelength using a cell merging technique. VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings. editor / Carolina Metzler ; Giovanni De Micheli ; Pierre-Emmanuel Gaillardon ; Carlos Silva-Cardenas ; Ricardo Reis. IEEE Computer Society, 2019. pp. 329-334 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

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abstract = "The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate's Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5 and 4.2 on average, respectively.",

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author = "Albinagorta, {Kevin A.Caceres} and Calebe Conceicao and Cardenas, {Carlos Silva} and Ricardo Reis",

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Albinagorta, KAC, Conceicao, C, Cardenas, CS & Reis, R 2019, Exploring area and total wirelength using a cell merging technique. in C Metzler, G De Micheli, P-E Gaillardon, C Silva-Cardenas & R Reis (eds), VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings., 8920337, IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, vol. 2019-October, IEEE Computer Society, pp. 329-334, 27th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cuzco, Peru, 6/10/19. https://doi.org/10.1109/VLSI-SoC.2019.8920337

Exploring area and total wirelength using a cell merging technique. / Albinagorta, Kevin A.Caceres; Conceicao, Calebe; Cardenas, Carlos Silva et al.
VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings. ed. / Carolina Metzler; Giovanni De Micheli; Pierre-Emmanuel Gaillardon; Carlos Silva-Cardenas; Ricardo Reis. IEEE Computer Society, 2019. p. 329-334 8920337 (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC; Vol. 2019-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate's Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5 and 4.2 on average, respectively.

AB - The industry of Integrated Circuits (ICs) has been making increasingly complex chips with up to billions of transistors in a single die. As we cannot do the design flow by hand, the leading adopted solution to deal with this challenge has been to use a pre-designed library of standard cells and using EDA tools to automate the process. Nevertheless, the resulting netlist is not as efficient in terms of the number of transistors as a handmade design, possibly reflecting in the overall area, power, and delay of the circuit. To generate cells on-demand is a way to improve this inherent limitation, as previous works demonstrate. In this paper, we investigate a netlist optimization methodology based on gate merging and its impacts regarding area and wire-length when applied to the Nagate's Open Cell Library for 45nm. We obtained a reduction in area and total wire-length of 3.5 and 4.2 on average, respectively.

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Albinagorta KAC, Conceicao C, Cardenas CS, Reis R. Exploring area and total wirelength using a cell merging technique. In Metzler C, De Micheli G, Gaillardon PE, Silva-Cardenas C, Reis R, editors, VLSI-SoC 2019 - 27th IFIP/IEEE International Conference on Very Large Scale Integration, Proceedings. IEEE Computer Society. 2019. p. 329-334. 8920337. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC). doi: 10.1109/VLSI-SoC.2019.8920337

Exploring area and total wirelength using a cell merging technique

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