Design of a CMOS cross-coupled voltage doubler

Luis Rodriguez; Erick Raygada; Carlos Silva; Julio Saldana

doi:10.1109/ANDESCON.2016.7836258

Design of a CMOS cross-coupled voltage doubler

Luis Rodriguez, Erick Raygada, Carlos Silva, Julio Saldana

Sección de Ingeniería de Telecomunicaciones

Pontifical Catholic Univ. of Peru

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

This paper describes a design procedure for a CMOS voltage doubler. Test-bench circuit are used to verify the performance of the design. Several equations that relate performance parameters with design variables are presented. This set of equations considers both transient and steady state behavior. Various known energy losses such as switching and conduction losses were taken into account for transistors sizing. The effects of the characteristics of the pump capacitors are analyzed and evaluated through electrical simulations. A design example based on AMS 0.35μm process is presented.

Original language	English
Title of host publication	Proceedings of the 2016 IEEE ANDESCON, ANDESCON 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781509025312
DOIs	https://doi.org/10.1109/ANDESCON.2016.7836258
State	Published - 27 Jan 2017
Event	2016 IEEE ANDESCON, ANDESCON 2016 - Arequipa, Peru Duration: 19 Oct 2016 → 21 Oct 2016

Publication series

Name	Proceedings of the 2016 IEEE ANDESCON, ANDESCON 2016

Conference

Conference	2016 IEEE ANDESCON, ANDESCON 2016
Country/Territory	Peru
City	Arequipa
Period	19/10/16 → 21/10/16

Keywords

charge pump
control-gate circuit
cross-coupled
design procedure
losses energy
voltage doubler

Access to Document

10.1109/ANDESCON.2016.7836258

Cite this

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title = "Design of a CMOS cross-coupled voltage doubler",

abstract = "This paper describes a design procedure for a CMOS voltage doubler. Test-bench circuit are used to verify the performance of the design. Several equations that relate performance parameters with design variables are presented. This set of equations considers both transient and steady state behavior. Various known energy losses such as switching and conduction losses were taken into account for transistors sizing. The effects of the characteristics of the pump capacitors are analyzed and evaluated through electrical simulations. A design example based on AMS 0.35μm process is presented.",

keywords = "charge pump, control-gate circuit, cross-coupled, design procedure, losses energy, voltage doubler",

author = "Luis Rodriguez and Erick Raygada and Carlos Silva and Julio Saldana",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE ANDESCON, ANDESCON 2016 ; Conference date: 19-10-2016 Through 21-10-2016",

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doi = "10.1109/ANDESCON.2016.7836258",

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Rodriguez, L, Raygada, E, Silva, C & Saldana, J 2017, Design of a CMOS cross-coupled voltage doubler. in Proceedings of the 2016 IEEE ANDESCON, ANDESCON 2016., 7836258, Proceedings of the 2016 IEEE ANDESCON, ANDESCON 2016, Institute of Electrical and Electronics Engineers Inc., 2016 IEEE ANDESCON, ANDESCON 2016, Arequipa, Peru, 19/10/16. https://doi.org/10.1109/ANDESCON.2016.7836258

Design of a CMOS cross-coupled voltage doubler. / Rodriguez, Luis; Raygada, Erick; Silva, Carlos et al.
Proceedings of the 2016 IEEE ANDESCON, ANDESCON 2016. Institute of Electrical and Electronics Engineers Inc., 2017. 7836258 (Proceedings of the 2016 IEEE ANDESCON, ANDESCON 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of a CMOS cross-coupled voltage doubler

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AU - Silva, Carlos

AU - Saldana, Julio

PY - 2017/1/27

Y1 - 2017/1/27

N2 - This paper describes a design procedure for a CMOS voltage doubler. Test-bench circuit are used to verify the performance of the design. Several equations that relate performance parameters with design variables are presented. This set of equations considers both transient and steady state behavior. Various known energy losses such as switching and conduction losses were taken into account for transistors sizing. The effects of the characteristics of the pump capacitors are analyzed and evaluated through electrical simulations. A design example based on AMS 0.35μm process is presented.

AB - This paper describes a design procedure for a CMOS voltage doubler. Test-bench circuit are used to verify the performance of the design. Several equations that relate performance parameters with design variables are presented. This set of equations considers both transient and steady state behavior. Various known energy losses such as switching and conduction losses were taken into account for transistors sizing. The effects of the characteristics of the pump capacitors are analyzed and evaluated through electrical simulations. A design example based on AMS 0.35μm process is presented.

KW - charge pump

KW - control-gate circuit

KW - cross-coupled

KW - design procedure

KW - losses energy

KW - voltage doubler

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T3 - Proceedings of the 2016 IEEE ANDESCON, ANDESCON 2016

BT - Proceedings of the 2016 IEEE ANDESCON, ANDESCON 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2016 IEEE ANDESCON, ANDESCON 2016

Y2 - 19 October 2016 through 21 October 2016

ER -

Design of a CMOS cross-coupled voltage doubler

Abstract

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Keywords

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