CMOS encoder for scale-independent pattern recognition

Julio Saldãa-Pumarica, Emilio Del-Moral-Hernández, Carlos Silva-Cárdenas

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The present paper reports the design of a CMOS circuit capable of codifying the natural logarithm of an analog voltage in the relative phase of a train of pulses. The circuit is aimed to the implementation of a scale-independent pattern recognition system, based on the explanation provided by J. Hopfield for the human brain pattern-recognition computation in terms of stimuli representation through the phase of the action potentials. The circuit is designed targeting the AMS 0.35 m process, occupying a core area of 0.0049 mm2 and with a power consumption of less than 14 W at a clock frequency of 3.3 MHz. The circuit codifies analog input voltages ranging form 1 to 5 V in phase differences between 2 and 2.7 s.

Original languageEnglish
Title of host publicationProceedings - SBCCI 2007
Subtitle of host publication20th Symposium on Integrated Circuits and System Design
Pages241-244
Number of pages4
DOIs
StatePublished - 2007
EventSBCCI 2007: 20th Symposium on Integrated Circuits and System Design - Copacabana, Rio de Janeiro, Brazil
Duration: 3 Sep 20076 Sep 2007

Publication series

NameProceedings - SBCCI 2007: 20th Symposium on Integrated Circuits and System Design

Conference

ConferenceSBCCI 2007: 20th Symposium on Integrated Circuits and System Design
Country/TerritoryBrazil
CityCopacabana, Rio de Janeiro
Period3/09/076/09/07

Keywords

  • Logarithmic encoding
  • Neuromorphic
  • Pulsed neural network

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